Zedboard Audio Hardware design (2/2)

Zedboard audio system block design

Summary

This is hardware designing part (2/2) of whole Zedboard audio system designing. In last article, I explained how to design audio hardware for Zedboard. The focus of this section will be more of generating bitstream file and device tree sources.

Logical Synthesis

When the design is done, this design has to be converted to the actual logic. This step will generate the logic which can be implemented on FPGA.

Click “Run Synthesis” button in left pane (Indicated in red square).

Logical synthesis

This takes a while. If something in the design is wrong, this reports errors.

If nothing is wrong, and the logic is synthesized properly, it’ll ask “Run Implementation”, but cancel this. Because, the logical design is done at this moment, but we haven’t assigned all the inputs/outputs from this logic, to the actual pins on the chip. To do this, click “Open Elaborated Design”.

IO port mapping

You will see “IO Ports” tab at the bottom. All the inputs/outputs should be appearing here. Before doing this, open the “Zedbaord hardware user guide”, and go to the Audio CODEC section. You will see “Table 9” below.

Audio CODEC connections in Zedboard

This tells you which pin on Zynq chip is connected to which pin of the Audio CODEC LSI. Connect those pins appropriately (fill “Package Pin” column for all inputs/outputs listed there).

NOTE: All DDR and FIXED_IO related ports are automatically connected to appropriate pins, and configured to the appropriate I/O standard. DON’T TOUCH those.

I/O Std settings

When everything is connected, it looks like picture above.

CAUTION: Here’s one critical thing. “I/O Std” column MUST BE CONFIGURED APPROPRIATELY. By default, it’s configured as “LVCMOS18”, which means, this pin will be configured as “1.8V CMOS input/output”. But this case, correct configuration is “LVCMOS33”, which is “3.3V CMOS input/output”. As you may see, the voltage is different, meaning that, if it’s configured wrongly, this might actually damage/break the hardware.

Implementation

When I/O ports are configured, we can implement this design. What implementation does is, this assigns hardware resources like LUT (Look Up Table) on FPGA to synthesized logic, and route all signals.

Click “Run Implementation” in left pane. This might re-run synthesis, and takes a while.

When this is done, it might raise warnings like “timing doesn’t meet”. This is because connection automation. It might connect “reset” “clock” signals to the wrong spots. In this case, check;

• “slowest_sync_clock” in all the System Reset block are connected to appropriate clock (100MHz, 48MHz, and 24MHz).
• All the reset signals are routed as expected.
• All the clocking signals are connected to appropriate ports.

I fixed few connections automatically made, and then, all the warnings have gone.

Bitstream generation

This step will generate binary file which can be downloaded to FPGA. Click “Generate Bitstream” at bottom left, or “File” -> “Export” -> “Export Bitstream”.

Device tree generation

Since we’ve used many Xilinx IP core, device tree for those IP cores can be generated automatically using Vitis (or Xilinx SDK in the past). In this case, we need to hand final hardware design to Vitis. To do this, select “File” -> “Export” -> “Export Hardware”. It will generate <file name>.xsa (if you are using older version, this might be something.hdf). Also, to generate device tree automatically, we need device tree generator published from Xilinx.

https://github.com/Xilinx/device-tree-xlnx

Vitis runs on my machine, but GUI doesn’t look really stable. I would use command line tools, which look bit more stable. Add the path to the Vitis executables, then type command below.

xsct

It will show CLI of the SDK tool. Type following commands.

hsi open_hw_design <path to XSA file>/<hardware>.xsa
hsi set_repo_path <path to device tree generator>/xlnx-device-tree
hsi create_sw_design device-tree -os device_tree -proc ps7_cortexa9_0
hsi generate_target -dir <target directory>
exit

This will create the directory which contains device tree sources.

Fix bugs in device tree

This device tree generation is very useful, but it has known bugs. It hasn’t been fixed for a long time.

1. include

Open “system-top.dts” in generated directory, and you will see something like below;

#include "zynq-7000.dtsi"
#include "pl.dtsi"
#include "pcw.dtsi"

This “include” syntax is wrong. Replace it with lines below.

/include/ "zynq-7000.dtsi"
/include/ "pl.dtsi"
/include/ "pcw.dtsi"

2. Write protect for MMC devices

By default, for some reason, SD card devices have “write protect”, and because of this, bootloader can’t boot from SD properly. Fix this by adding “disable-wp;” line in zynq-7000.dtsi like below;

sdhci0: mmc@e0100000 {
    compatible = "arasan,sdhci-8.9a";
    status = "disabled";
    clock-names = "clk_xin", "clk_ahb";
    clocks = <&clkc 21>, <&clkc 32>;
    interrupt-parent = <&intc>;
    interrupts = <0 24 4>;
    reg = <0xe0100000 0x1000>;
    disable-wp;
};
sdhci1: mmc@e0101000 {
    compatible = "arasan,sdhci-8.9a";
    status = "disabled";
    clock-names = "clk_xin", "clk_ahb";
    clocks = <&clkc 22>, <&clkc 33>;
    interrupt-parent = <&intc>;
    interrupts = <0 47 4>;
    reg = <0xe0101000 0x1000>;
    disable-wp;
};

We still need to modify device tree (because we have devices like Audio CODEC outside the Zynq SoC), but this will be another topic.

Summary

In this section, we completed the hardware designing part, and generated output files like below;

• Bitstream (<hardware>.bit)
• Device tree source directory

Those will be needed in later phase.