Basic Standalone Hardware Designing
Preface
In this section, the focus will be on the flow of designing standalone hardware using Xilinx Vivado. Basic logic designing and HDL (Hardware Description Language) will be introduced in different section.
In this example, to make things very simple, processing system (PS) won’t be added. Therefore, there will be no software work.
Creating and testing 4 bit adder
Here is an HDL (Verilog) of 4 bit adder. This module has 4 bit inputs a and b, and 5 bit output y. It calculates the sum of a and b in binary, then output it to y (y = a + b). How to make this HDL working on FPGA using Vivado will be the focus on this example.
Creating project in Vivado
Launch Vivado (I’m using Vivado 2017.4), and Select “Create Project”.
Specify the project location, and project name, then “Next”.
Select “RTL Project” and “Next”.
In this example, adder4.v is already prepared. So the source code is simply added (Add Files). But it can be blank and code can be added later.
In this example, constraints file for adder4 (adder4.xdc) is already prepared. You can leave it blank since this is optional.
You have to choose default part. You want to get “Board definition” for your specific board to make auto connection working. If your board doesn’t appear in the window, then you have to visit this site and get board definitions.
https://github.com/Digilent/vivado-boards
How to install board definitions are described well here.
After clicking “Finish” button, you will see the project window.
Edit Constraints
In the HDL file, there are several inputs (a and b, both 4 bits) and outputs (y, 5 bits) defined, but to which pins those should be connected are not defined. Those connections between input and output in HDL, and the physical pins in actual device are described in “constraints” file. Constraints include various other things, but in this example, all we have to care are physical pin assignments and electrical character of each pin (Voltage, pull-up, etc.).
To edit constraints, we need to elaborate design. Click “Open Elaborated Design” under RTL ANALYSIS tab. After few moment, you will see I/O ports at the bottom.
In this field, you need to edit;
- Package pin … Assignment of physical pin
- I/O Std … Electrical Characteristic
You need to look at the hardware manual of the target board, and then connect those inputs and outputs correctly. In this example, input a[4] and b[4] are connected to the slide switches, and output y[5] are connected to the 8-bit LEDs. Click the arrow beside “a”, to break it down, then edit individual pin assignment. In this example, the voltage of the I/O pins are all 1.8V. So LVCMOS18 in I/O Std field is selected.
Synthesis, Implementation and bit stream Generation
After creating the project, and adding source codes, what we need to make this design working on actual device (FPGA) are 3 things listed below;
- Synthesis
- Implementation
- Bit Stream Generation
Synthesis will generate the “logic” which works as described in HDL source code. The description in HDL files are called RTL (Register Transfer Level) description, and it doesn’t have to match the actual logic. This is especially true when the RTL is described in high level language like System C. Synthesis will convert those behavioral description into actual logic.
To initiate this process, click “Run Synthesis” button in Vivado.
Implementation will assign actual resources in FPGA to make the logic (synthesized in previous step) working. Resources include LUTs, DSP slices, RAMs, Flip-Flops and so on. This step will place all the necessary parts, and connect everything correctly in FPGA. Implementation depends on FPGA device.
To initiate this process, click “Run Implementation” button in Vivado.
Lastly, click “Generate Bitstream” to generate the bitstream which can be downloaded into FPGA.
Download the bitstream to the FPGA
To download bit files to the FPGA, there are several ways to do that. But the simplest way is using JTAG (Joint Test Action Group) connection.
JTAG is used not only to download the bit stream to the device, but also used to debug the logic. Usually, there is an on-board USB-JTAG device. So you can simply connect to the device via USB.
You might need to install the USB-JTAG driver separately. In that case, follow this step.
- Connect to the board via USB-JTAG
- Check jumper pin settings (M102 — M106 should be grounded)
- Connect to the board and download bitstream via Vivado
Click “Open Hardware Manager” -> “Open Target” -> “Open New Target” at the bottom.
“Next”, then choose “Local Server” unless you are connecting to the remote server.
Once, the connection is established, then you can click “Program Device”.
When the program is completed correctly, blue LED labelled “DONE” will be on.
Let’s test the device. This is 4 bit adder, and the slide switches at the bottom can input binary. For example, let’s input 0b0100 (0x4) and 0b0110 (0x6) from switches. If the LED looks like 0b1010 (0xA), then the adder4 module is working as expected (try different combinations as well).
