In this section, the focus will be on generating synthesizer hardware bitstream for Zedboard. Entire system overview including software architecture is explained here.
Detail of the synthesizer hardware design is explained below.
Also, designed hardware Verilog source code is available here.
“src” folder includes all the modules instantiated in IP, “sim” folder has all the testbenches, and “hdl” folder contains top module of the IP.
As I explained before, CPU (ARM Cortex-A9 dual core) to run Linux will be needed in this project. Open Vivado, create new project for Zedboard…
VCA (Voltage Controlled Oscillator) controls the amplitude/volume of the tone. It’s not just the velocity of the note, but it changes the volume time to time, to simulate the actual musical instruments. To make this happen, EG (Envelope Generator) is also used. In this section, the focus is on the design of both EG and VCA.
The overview of entire synthesizer hardware is explained below.
To simulate the actual musical instruments, VCA changes the volume of the tone time to time. For example, instruments like piano, volume rises quickly since when the note is played, and…
In this section, I’ll explain the design of the VCO (Voltage Controlled Oscillator) in synthesizer hardware. VCO basically is a wave generator. Overview of the synthesizer hardware is explained below.
Figure 2 shows various wave types which can be generated by this VCO.
In this section, both hardware and software implementation of Zedboard digital musical synthesizer will be explained. Each chapter (“Hardware Designing” and “Software Designing”) will have links to design overview, and details of each component design.
In this article, what are already existing, and what are newly added will be explained (scope of this personal project).
Figure 1 shows the hardware block diagram of the entire synthesizer hardware. Detail of the synthesizer hardware design is explained here.
For this project, I chose Digilent Zedboard as the target board. Detail of the Zedboard is available below.
Digital hardware are composed of 2 different kinds of components;
State machine is quite important to make complicated hardware like multiplier, divider, control logic of the processor (CPU), and so on. In this section, an overview of the state machine, and how it’s described with HDL (Hardware Description Language) will be explained.
As the name suggest, state machine has its “state”. In figure 1, there are 5 different state;
Time Division Multiplexing (TDM) is one of important techniques for digital hardware designing. This is useful to reduce the area and resource usage in a circuit.
TDM is used to reduce the size of the circuit. Figure 1 shows the overview of TDM. Suppose, input A — D, and output A — D are data stream… for example, audio data, video data, or maybe internet traffic. Input keeps coming in, and output are usually synchronous with the input, and it keeps going out. To process data stream A — D in parallel, process units must be duplicated like upper half…
In this section, how digital divider calculates quotient and remainder will be explained. Also, how this can be implemented on FPGA will be shown with some experimental results.
Figure 1 shows the decimal division calculation. How decimal division works is like below.
I needed to design 32-bit multiplier for another personal project. So I googled and did some experiments with multipliers on FPGA (Zedboard). I’ll show the results of my experiments.
Figure 1 shows decimal and binary product calculation. First example is calculation in decimal (1234 X 5678). This is calculated like below.
That’s how humans calculate the product in decimal. It’s same for binary, but much simpler, since there are only two numbers: 0 and 1…
In this chapter, I’ll explain how the computer hardware is calculating “a - b”. To understand how subtractor works, binary adder has to be understood. This is explained in the past article.
In the computer hardware, subtraction is calculated differently. I’ll show example using decimal number.
We’ll calculate “7 - 3” like computer. First, we need to find the number which is called 10’s compliments. Compliment of 3 is calculated like below.
3 + X = 10
X = 10 - 3
So 10’s compliment of 3 is 7. Next, add this number…